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the goal is, i want to have a module which can be dynamically enabled and disabled as a janky write protect mechanism
basically once enabled any writes in a certain address range should generate a reset

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question for hardware folks:

i want to do something extremely fucking cursed and i want to know if it's feasible

so, the zynq-7000 soc series has arm cores with a xilinx fpga, and importantly the arm core contains the ddr controller
however for some reason you connect the ddr controller to the actual ram through the fpga fabric
so i want to know, can i make an fpga module that goes in between and sniffs the dram traffic? like figure out if there are reads or writes generated in certain address ranges?


whoops is it bad that i can recognize suzushiro333 art like literally instantly

so the other interesting fpga thing that i don't have answers on is
can you "cold boot" the block ram
there's like absolutely nothing abt this on the line so i think we're gonna have to do a manual test

breaking news: local enby does a slep
they are rly comf and zzz

dubiozaposting, loud 

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dubiozaposting, loud 

hackers have some sort of mindset that for some reason a lot of ppl in computers choose not to have
i think it's just the idea that `you _can_ actually do the thing` which i basically only picked up like 3 years ago
but i actually don't know it's kind of interesting

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slightly related i go hhh for people i can trust to write good code
ppl who write good code tend to tell me they write bad code and this is kind of a paradox of people who care enough about their own code quality to say that
so like no, your code is actually rly good because you paid attention to proper swe practices and tried to make it good

tbh i'll probably immediately piss off eece people if i enter like a 20m radius because i just have no hecking idea what i'm doing lol

but that's okay we'll figure it outβ„’

whoops i bootstrapped a basic understanding of dram in like an hour

i still don't know how exactly addresses on this chip map to banks and rows and columns (and there's a thing i've heard of called `swizzling` which may make that complicated) or even if this whole idea is just garbage or not

anyway the other big issue is the fpga max clock is 250mhz and the dram is 525mhz so we're gonna have to underclock that,

i feel like i'm the only person on this hecking planet who now knows and actively uses both racket and vhdl

i like how i'm just The Fpga Person now
despite not knowing like anything about fpgas

dram posting 

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