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So my HDL playing has been partially converting nand2tetris HDL into actual Verilog so that I can hopefully put it on an actual FPGA, and I've managed to get as far as loading my ALU into yosys and generating a nice diagram of it and y'all, it looks pretty rad! Check it out!

(Spoilers for I guess, don't look too closely if you don't want to know how I put my ALU together!)

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