I picked up an old book of "Everyone's Favorite Piano Pieces" from 1933, and this arrangement of In the Hall of the Mountain King is a trip. It literally starts at B0 (that's the third key from the bottom of a standard keyboard) and eventually ranges up to D#7, which is 10 keys from the top. Phew!

Just spent like 20 minutes trying to figure out why the heck my mouse pointer was jumping around randomly. Got as far as monitoring the output of /dev/mice before I finally realized I still had my drawing tablet plugged in and buried under a pile of paper, so it was just getting confused as heck 🤦‍♂️

Best part, I had just moved from my laptop to the desktop and this was also happening on my laptop, because I was running Synergy and the erratic mouse movements were getting sent over the network to my other computers!

Joel relayed

I have just launched a website inspired by pronoun.is for Spanish speakers:

prono.mbre.es/

I deployed using Hugo, GitHub and Netlify. Quite simple to set up and much easier to edit than plain HTML. I hope people like it ❤️

Joel relayed

@nihilazo So, uh, I got thinking about the two possible answers that aren't in the poll, and that resulted in an alignment chart, of course:

Cackling as I bring std::variant, std::visit, snprintf, and strtok into the list of things I am absolutely desecrating in this project. It really is becoming a monument to doing things in the worst way possible.

Current status on my HDL adventures: generating C++ code with Awk so I can get around not having reflection in this Verilator code I'm writing.

This project just doesn't stop giving! 😄

Joel relayed

I guess as a more general question: are there any guides on making command line tools more accessible? Just a command with feedback and the occasional confirmation prompt, not like a while interactive thing

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Gonna take some more runs at beating The Radiance in , streaming on my at stream.cincodenada.com

Come on over and hang out if you want!

Joel relayed

I was already intrigued by Hey but feeling like it was too one-size-fits-all for my needs, so with the big Basecamp "our employees aren't allowed to be people unless they like the status quo" nonsense, I'm doing a little, uh, reorganizing of my Fastmail to see if I can arrange it to better meet my needs without Hey:

Today my yak stack has been materialized into pull requests, and I am now four pull requests deep, each depending on the next one down in the stack.

Delightfully, the issue numbers for these PRs (one issue has two PRs) are 2825, 2845, and 2895.

Dependency management is fun!!!! :blobdisapproval:

Joel relayed
Joel relayed

Social anxiety is:

Editing a slack message containing only the word "yes" twice to get the tone just right.

Joel relayed

с днём рождения, кот с блинами! \^o^/

RT @scoobs_online@twitter.com

blini cat is 10 years old today everybody say happy birthday blini cat

🐦🔗: twitter.com/scoobs_online/stat

Joel relayed

New shot today. 4x zoom. Really happy with the results. Almost finished with editing. #theObservatory

By golly, it works! I'm venturing into FPGA-land, and managed to write and program a very basic program to my dev board. The program is literally this:

module buttons(
input [0:7] buttons,
output [0:7] leds
);
assign leds=buttons
endmodule

Which simply connects each button to its respective LED. But the important part is I got it built, synthesized, placed and routed, and programmed! I even connected the ports to the right pins, and look! It does a thing!

So this computer had decided to bail into intramfs a few days ago, and after it wouldn't boot from USB, I managed to recover it from intramfs by mounting my root fs, pulling fsck off of it into the tmpfs, then unmounting and running fsck on it. Feeling very wizardy today! 👨‍💻

Joel relayed

Anyone from North or South America? Please give uberspace.de a quick ping in your terminal or GUI tool. We're interested in latency, your very rough location, and optionally ISP. Thanks :)
(boosts for sample size very welcome!)

So my HDL playing has been partially converting nand2tetris HDL into actual Verilog so that I can hopefully put it on an actual FPGA, and I've managed to get as far as loading my ALU into yosys and generating a nice diagram of it and y'all, it looks pretty rad! Check it out!

(Spoilers for I guess, don't look too closely if you don't want to know how I put my ALU together!)

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